The present invention relates to analog-to-digital conversion (ADC) circuitry, and in particular, to continuous time sigma delta ADC circuitry.
As signal conversion and processing rates have increased dramatically within today's digital systems, conversion rates for analog signals to digital signals have increased dramatically. To achieve the necessary conversion rates, sigma delta ADC circuits are often used, with one example being a continuous time sigma delta ADC circuit.
Referring to FIG. 1, a conventional continuous time sigma delta ADC circuit 10 includes mixer circuitry 12, and the continuous time sigma delta ADC circuit 16, between which a voltage-to-current conversion circuit 14 (e.g., buffer and/or filter circuitry) is used. As is well known in the art, the mixer circuitry 12 mixes the incoming analog signal 11i with a local oscillator, or clock, signal 11c (e.g., as part of a quadrature signal conversion). The mixer circuitry 12 is generally operated in such a manner as to convert the input current signals 11i, 11c to a voltage mode signal as the resulting mixed, or product, signal 13.
However, conventional continuous time sigma delta ADC circuits 16 operate with A current mode input stage. Accordingly, the voltage mode mixed signal 13 must be converted to a current mode signal 15. This is achieved by the voltage-to-current conversion circuit 14, in accordance with principles well known in the art.
A problem associated with this type of implementation is the overhead, e.g., in terms of circuit elements and power requirement/dissipation, associated with the current-to-voltage conversion of the mixer circuitry 12 and the voltage-to-current conversion circuitry 14 necessary to ultimately provide a current mode signal 15 for the sigma delta ADC circuitry 16, even though the original input signals 11i, 11c were already current mode signals. Accordingly, it would be desirable to minimize or even avoid such overhead.